The field programmable gate array (FPGA) has enjoyed popularity as application-specific integrated circuits (ASICs) due to its advantages of relatively high gate density, short design cycle, and low cost. Due to its field-programmable capability, the FPGA has been widely used to replaced small and medium-scale integration devices (SSI and MSI), programmable logic devices (PLDs), and mask-programmable gate arrays in applications that do not require a very large number of gates and very high speed. FPGAs are also used to build prototypes of high density, high speed custom chips and ASIC devices in which a number of FPGAs may be used for emulation purposes.
A typical FPGA architecture is composed of a two-dimensional array of logic modules that may be selectively connected with vertical and horizontal tracks. The logic modules may be arranged in a matrix or in rows and columns. In the row/column-based FPGA architecture, the antifuse is the programming element which interconnect the logic modules. Two adjacent segments of horizontal/vertical routing tracks may be connected by programming a horizontal/vertical antifuse. Antifuses are also positioned at intersections of vertical and horizontal tracks to route signals from horizontal tracks to vertical tracks or vice versa.
To program an antifuse, a predetermined amount of programming current, I.sub.SOAK, is passed through the device. In addition, there is an upper limit, I.sub.PEAK, on the amount of current that is permitted to pass through the antifuse. Traditionally, a typical widely used antifuse device has had very attractive parameters (low resistance and capacitance) compared to other FPGA programming technologies such as SRAM based devices, hence allowing much faster and smaller programming technology. The newer types of antifuses that are gaining popularity rapidly, have even more attractive on-state-resistances and loading capacitances. However, as the antifuse technology progresses, the I.sub.PEAK to I.sub.SOAK ratio becomes more critical. An example of such an antifuse device is the amorphous silicon antifuse. In the high performance amorphous silicon antifuse device, unpredictable and undesirable behavior is observed when the ratio of I.sub.PEAK to I.sub.SOAK exceeds a certain threshold.
Various methods have been explored to limit the current passing through the amorphous silicon antifuse. One proposal increases the resistance in each antifuse. The result is significant speed degradation of the FPGA. At the output of each logic module is an output driver which drives the lines or tracks that the antifuses are located. Some have attempted to limit the antifuse current by putting restrictions on the output driver. For example, one method limits the fanout of output drivers of each logic module, and another scales down the size of the output drivers. When the output drivers are required to provide less fanout, or its size is scaled back, the amount of current drawn by the output driver decreases and thereby decreasing the current through the antifuse. However, these methods either put unacceptable limitations on the device architecture or adversely affect the speed of the device. Additional output buffers have also been added to the logic modules to decrease the amount of output current from each driver with the unacceptable result of requiring potentially large real estate for the added circuit and routing lines. Yet another method, decreasing the voltage swing at the output of the logic modules, adversely impacts the speed of the FPGA device.
Accordingly, a need has arisen for a method or circuit arrangement that reduces the maximum current through the antifuse without any speed degradation and large penalty on real estate.